The present invention relates to a semiconductor device and is suitably applicable to, for example, a semiconductor device using a fin type field-effect transistor (FET).
It is important to keep a setup time and a hold time of a data signal within predetermined ranges in a timing design of a semiconductor integrated circuit which operates synchronously with a clock. For this reason, in commonly used semiconductor integrated circuit, the timing is adjusted by providing a plurality of data buffers in series in a data signal line (for example, see Japanese Unexamined Patent Publication No. Hei 7(1995)-66293 [Patent Document 1]).
[Patent Document]
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 7(1995)-66293